NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable ProcessorsĬheung, Kit Schultz, Simon R. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms.
A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.Ĭheung, Kit Schultz, Simon R Luk, Wayne Each AAC NNP module has 8 K neurons and 32 K interconnections and is capable of 140,000,000 connections per second with an eight processor array capable of over one billion connections per second.
HYPERSWITCH TORRENT UPDATE
Moreover, by using a MIMD parallel processing architecture one can update multiple neurons in parallel with efficiency approaching 100 percent as the size of the network increases. The AAC NNP design fully exploits the intrinsic sparseness of neural network topologies. The Accurate Automation Corporation (AAC) neural network processor (NNP) module is a fully programmable multiple instruction multiple data (MIMD) parallel processor optimized for the implementation of neural networks.
Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.ĭesign of a MIMD neural network processor The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports.
The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. (Inventor)Ī connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. Operations performed by the processor network include simulation of the motion and d.Īrray processor architecture connection networkīarnes, George H. INPUT PROCESSOR NETWORK DESIGNĭetailed specifications are given for a network of data processors and submodels that can generate the parameter fields required by the regional oxidant model formulated in Part 1 of this report. REGIONAL-SCALE (1000 KM) MODEL OF PHOTOCHEMICAL AIR POLLUTION.
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